The invention relates generally to the field of power over local area networks, particularly Ethernet based networks, and more particularly to a method and apparatus arranged to allow for multiple independent powered device to support a single load.
Power over Ethernet (PoE), in accordance with both IEEE 802.3af-2003 and IEEE 802.3at-2009, each published by the Institute of Electrical and Electronics Engineers, Inc., New York, the entire contents of each of which is incorporated herein by reference, defines delivery of power over a set of 2 twisted wire pairs without disturbing data communication. The aforementioned standards particularly provide for a power sourcing equipment (PSE) and a powered device (PD). The power sourcing equipment is configured to detect the PD by ascertaining a valid signature resistance, and to supply power over the 2 twisted wire pairs only after a valid signature resistance is actually detected.
The HD BaseT Alliance of Beaverton Oreg. has published the HDBaseT Specification Version 1.1.0 which defines a high power standard utilizing twisted wire pair cabling, such as Category 5e (CAT 5e) or Category 6 (CAT 6) structured cabling as defined by ANSI/TIA/EIA-568-A. The specification provides for even higher power than the above mentioned IEEE 802.3at-2009 over each set of 2 pairs, with all 4 pairs utilized for powering, and allows for power over structured communication cabling from any of: a type 1 PSE, denoted hereinafter as a low power PSE, typically meeting the above mentioned IEEE 802.3af standard; a type 2 PSE denoted hereinafter as a medium power PSE, typically meeting the above mentioned IEEE 802.3at standard; a type 3 PSE, denoted hereinafter as a high power PSE, typically meeting the above specification; twin medium power PSEs; and twin high power PSEs.
U.S. Pat. No. 7,509,114 issued Mar. 24, 2009 to Berson et al., the entire contents of which is incorporated herein by reference, is addressed to a redundant powering system. In such a system power is actively supplied to the load by a first PSE, with a second PSE acting in a standby capacity. Both the first PSE and the second PSE area connected to the PD over a single communication cabling.
U.S. Pat. No. 7,449,796 issued Nov. 11, 2008 to Elkayam et al., the entire contents of which is incorporated herein by reference, is addressed to a PoE controller supporting a plurality of modes, where a pair of PSEs may supply power in combination to a single PD, or to independent PDs.
FIG. 1 illustrates a high level block diagram of a PoE powering arrangement 10, according to the prior art, comprising: a first PSE 20, denoted PSE1; a second PSE 20, denoted PSE 2; a first and a second communication cabling 30; a first PD 40, denoted PD1; a second PD 40, denoted PD2; a first and a second ORing diode 50; a first maintain power signature resistor MPS1; a second maintain power signature resistor MPS2; and a load 60. PSE1 is coupled via first communication cabling 30 to PD1 and PSE2 is coupled via second communication cabling 30 to PD2, with each communication cabling typically comprising 4 twisted wire pairs, such as a CAT 5 or CAT 6 cable, as is known to those skilled in the art. In the particular embodiment shown, each PSE 20 is coupled to a respective PD 40 over a particular communication cabling 30, however use of a single communication cabling 30 for coupling a pair of PSE 20 to a pair of PDs 40 may also utilized without exceeding the scope.
The output of each PD 40 is coupled via a respective ORing diode 50 to the positive terminal of load 60, and the return terminal of load 60 is coupled to the return of each PD 40. Thus, the PD 40 exhibit the higher voltage will power load 60, and the PD 40 with a lower voltage will be cut-off by the operation of ORing diodes 50. First and second maintain power signature resistors MPS1, MPS2, respectively, ensure that a sufficient load is presented to each of PD1 and PD2 so as to ensure that the respective PSE 20 does not disable power due to an under load condition. While maintain power signature resistors are shown, this is not to be limiting in any way, and a controlled current source, or toggled resistances may be utilized without exceeding the scope. The input of load 60 typically provides a bulk capacitor, which as will be described further below requires charging under inrush current controlled condition.
FIG. 2 illustrates a high level block diagram of PD 40 and associated input circuitry, according to the prior art, and is available commercially as PD70200 from Microsemi Corp., of Aliso Viejo, Calif. The input circuitry typically comprises a pair of center tapped data transformers, and respective diode bridges, or ideal diode bridges, so as to ensure that PD 40 may receive power under either ALT-A or ALT-B connection, in accordance with the above mentioned standards, irrespective of polarity. For simplicity, the input circuitry is illustrated as respective full wave bridges 100. PD 40 comprises a field effect transistor 110, shown as an NMOSFET; a sense resistor RS; and a PD control state machine 120. PD control state machine 120 comprises: a detection functionality 130, arranged to provide a predetermined resistance to PSE 20 responsive to a detection voltage; a class functionality 140, arranged to provide a predetermined class current towards the respective PSE 20 in response to a classification voltage; current limit functionality 150 arranged to control NMOSFET 110 so as to ensure that current flow does not exceed certain limits responsive to current flow detected as a voltage drop across sense resistor RS; and a temperature detection functionality 160 to prevent overheating.
In operation, PSE 20 provides an initial detection voltage, typically as a plurality of voltage levels less than 10 V, and upon successful detection of the appropriate resistance of detection functionality 130, presents a classification voltage to PD 40. Optionally, detection functionality 130 is switched out of the circuit responsive to PD control state machine 120 responsive to the detected voltage, which is now in excess of the detection voltage. Class functionality 140 provides a predetermined current flow, whose value may set responsive to an externally measured resistor, so as to identify the power requirement of PD 40 to PSE 20. PSE 20, responsive to a successful detection and optional classification, and if sufficient power is available, then raises the output voltage to an operating voltage, typically in excess of 30 Volts. PD control state machine 120, provides an initial current limit to current limit functionality 150, known as an inrush current limit, denoted ILIM-LOW to prevent a high inrush current upon initial powering due to the charging of any input capacitor at load 60. ILIM-LOW is typically about 240 mA. Upon sensing that the startup has completed, PD control state machine 120, provides an operating current limit functionality 150, higher than ILIM-LOW, the higher operating mode current limit denoted ILIM-HIGH, which is typically about 450 Ma for low current conditions, and may extend up to 1,800 mA for over current protection. In certain embodiments ILIM-HIGH is set to about 1,100 mA. Other values are also known to those skilled in the art, however the above values are illustrative. In the event of an over temperature condition detected by temperature detection functionality 160, PD control state machine 120 may open NMOSFET 110 to prevent any further flow of current.
The completion of startup is identified by PD control state machine 120 responsive to a reduction in current flow, as sensed across sense resistor RS, to a value below ILIM-LOW. Alternately, the voltage drop across NMOSFET 110 is measured, and upon detection that the voltage drop across NMOSFET 110 is below a value indicating that current flow is not restricted by NMOSFET 110, the completion of startup is identified by PD control state machine 120. In one embodiment, a voltage drop of less than 0.7 V across NMOSFET 110 is indicative that startup has completed and PD control state machine 120 thus changes provides operating current limit functionality 150 to ILIM-HIGH.
PoE powering arrangement 10 is illustrated as having a pair of PDs 40, however additional powering options may be provided without limitation. For example a mains power adapter may be provided, which preferably is set to output power at a voltage in excess of any expected output voltage from PD1 or PD2, and thus by virtue of a respective ORing diode 50 (not shown) take over powering of load 60 from either PD1 or PD2. In another embodiment a detection circuitry is provided associated with the mains power adapter. Upon detection of active power from such a mains power adapter, power is not drawn from either PD 1 or PD2, however responsive to first and second maintain power signature resistors MPS1, MPS2 both PSE 1 and PSE 2 remain active, i.e. they do not disable power due to an under load condition.
There is one difficulty in PoE powering arrangement 10, which unfortunately prevents its use. For ease of understanding, let us assume that one of the PSEs 20, say PSE1, is supplying power to PD1, at a first voltage level, for example 50 V, and load 60 is drawing 0.5 A. In the event that PSE2 is now enabled at a higher voltage, say 56 V, PD2 will be detected and powered, however PD2 will be unable to detect the end of startup, since it will unable to raise the voltage across load 60 to the higher operating voltage due to the low ILIM-LOW, which as indicated above is at about 0.24 A. Thus PD2 will latch in the startup mode and its internal switch may overheat due to continuing operation in linear mode.
What is desired is a solution to the above problem, preferably allowing the use of standard, commercially available PDs.